The present invention relates in general to data processing systems, and in particular, to cache event triggering in simulations of processor systems.
It is commonplace, in modern data processing systems, to include high speed memory, called caches, to improve the performance of memory transactions. Typically, the central processing unit (CPU) includes an amount of cache memory, which can be accessed by the processor core very quickly. This cache is commonly referred to as the level one (L1). Additional levels of cache, which may be either internal or external to the CPU, may be included between the L1 cache and main memory. A next level of cache is typically referred to as level two (L2) cache, and additional levels may be labeled in similar fashion.
CPU memory transactions cause traffic between the L1 and L2 caches, or more generally between lower level (LL) and higher level (LH) caches in a data processing system including multiple levels of cache memory. For example, a xe2x80x9ccastoutxe2x80x9d occurs when there is a cache miss in the L1 cache, and the cache line to be replaced, to make room for the line to be fetched from the L2 cache or main memory, has been modified. Then, the modified cache line is written to, or castout, to the L2 cache. Similarly, a xe2x80x9cpushxe2x80x9d operation occurs if a snoop hit is detected in which the snooped location corresponds to a modified line in the L1 cache. Then, the line is xe2x80x9cpushedxe2x80x9d to main memory or to the requesting bus device, which may be a second CPU in a multiprocessor system.
In a simulation environment, in order to fully simulate the L2 cache control logic, maximum traffic from the L1 cache to the L2 cache should be generated. Previously, either no cache model (an event generator that emulates any legal function of the cache) for providing maximum traffic was built into the L1 event generator (event generators are typically referred to as xe2x80x9cirritatorsxe2x80x9d), or a cache model for providing maximum traffic was implemented in the L1 imitator but encountered difficulties in providing maximum traffic because most of the data was cached in the L1 model, and cache block movement did not occur until a modified cache line was selected for replacement. Thus, in the latter case, L1 to L2 traffic was not generated until induced by the instruction stream in The test case under simulation. Consequently, in both circumstances, there are problems in generating sufficient traffic to ensure that xe2x80x9ccornerxe2x80x9d cases were covered. Corner cases refer to L2 control logic states that occur infrequently. Then, the simulations may fail to uncover cache flaws, or xe2x80x9cbugs.xe2x80x9d
Therefore, there is a need in the art for a mechanism to mitigate against untested comer cases. In particular, there is a need in the art for a cache irritator mechanism to generate traffic rates between cache levels, for example between L1 and L2 caches, sufficient to stress the cache control logic of the LH cache, and to generate critical block movements from the LL cache to the LH cache.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a method for cache model simulation. The method includes providing a predetermined set of cache block movement event protocols. An event protocol is selected from the predetermined set, and a castout of lines in a first cache is performed in response to the protocol.
There is also provided, in a second form, a data processing system for cache model simulation. The system contains circuitry operable for providing a predetermined set of cache block movement event protocols. Also included is circuitry operable for selecting an event protocol from the predetermined set, and circuitry operable for performing a castout of lines in a first cache in response to the protocol.
Additionally, there is provided, in a third form, a computer program product operable for storage on a machine readable storage medium, wherein the program product is operable for cache model simulation. The program product has programming for providing a predetermined set of cache block movement event protocols, and programming for selecting an event protocol from the predetermined set. Programming for performing a castout of lines in a first cache in response to the protocol is also included.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.